DFT Engineer

Job Description:

Responsibilities

• Implement and integrate scan insertion and scan compression at gate/RTL level.
• Support Scan ATPG, pattern validation, and silicon bring-up of scan-related DFT features.
• Perform gate-level verification, debug DFT/scan issues, and support ECOs.
• Develop and improve DFX/DFT methodologies for next-generation designs.
• Work closely with CAD and external CAD venders in developing next DFX architectures in nvidia chips
• Collaborate with design, verification, and physical design teams to ensure DFX readiness.

Qualification & Expeirence

• BSEE/MSEE or equivalent experience.
• 2+ years of experience in DFT/DFX implementation.
• Strong knowledge of ASIC design flow, static timing analysis, and ECO handling.
• Hands-on experience with gate-level simulation and verification.