Senior DFT Engineer

Job Description:

Responsibilities

• Architect, implement, and validate innovative DFT techniques on ARM SoCs. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.

Experience

• Core DFT skills considered for this position should include some of the following: Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics
• Experience ranges from 10- 20 Years.
• Experience coding Verilog RTL, TCL and/or Perl
• Proficient in Unix/Linux environments
• Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field