Mixed Signal Logic Verification Engineer

Job Description:

Responsibilities

• Strategy & Planning: Develop, implement, and lead comprehensive verification plans for Complex Mix Signal IPs.
• Methodology: Design and maintain advanced test benches, scoreboards, and checkers using System Verilog and UVM.
• Technical Leadership: Mentor junior engineers, conduct code reviews, and drive verification closure to meet project milestones.
• Debug & Analysis: Perform RTL debug, gate-level simulations, and functional/code coverage analysis.
• Collaboration: Work with architects and design teams to identify, debug, and resolve issues, including post-silicon failures.
• Formal Verification: Utilize formal methods (e.g., model checking) to verify complex, hard-to-reach corner cases.

Qualification & Experience

• Experience: 11-15 years of, or equivalent, experience in ASIC/SoC verification.
• Languages & Methodologies: Expert-level knowledge of System Verilog, UVM, and Verilog.
• Protocols: Proficiency in standard protocols like JTAG/IJTAG/CRI/APB and multi clock domain Mix signal designs.
• Tools: Hands-on experience with industry-standard EDA tools (Synopsys VCS, Cadence Xcelium/JasperGold, Mentor Questa).
• Scripting: Strong scripting skills (Python, Perl, Tcl) for testbench automation.
• Education: B.E/B.Tech or M.E/M.Tech/MS in Electronics/VLSI Engineering.
• Domain Knowledge: Expertise Mix signal Sensor IP verification.